Published in:   Vol. 6 Issue 2 Date of Publication:   December 2017

Page(s):   105-109 ISSN:   2278-2397

DOI:   10.20894/IJCOA.101.006.002.013 Publisher:   Integrated Intelligent Research (IIR)

• Abstract
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• References

D. Boning and S. Nassif,   "Models of process variations in device and interconnect",   IEEE Press   ,2000
View Artical


P. P. Pande, C. Grecu, M. Jones, A. Ivanov, and R. Saleh,,   "Performance evaluation and design trade-offs for network-on-chip interconnectarchitectures",    IEEE   ,Vol.54   ,Issue 8   ,2005
View Artical


M. Palesi, R. Holsmark, S. Kumar, and V. Catania,   "Application specific routing algorithms for networks on chip",    IEEE    ,Vol.20   ,Issue 3   ,2009
View Artical


C. Nicopoulos,   "On the effects of process variation in network-on-chip architectures,",    IEEE Trans. Dependable Secure Comput   ,Vol.7   ,Issue 3   ,2010
View Artical


S. Ranka,   "Contemporary computing,",   Communications in Computer and Information Science   ,Vol.40   ,2009
View Artical


Y. Markovsky, Y. Patel, and J. Wawrzynek,,   "Using adaptive routing to compensate for performance heterogeneity",   ACM/IEEE Int.Symp. Netw.-Chip   ,2009
View Artical


A.Sharifi and M. Kandemir,   "Process variation-aware routing in NoC based multicores",   ACM/EDAC/IEEE Design Autom   ,2011
View Artical


W. Dally and B. Towles,   " Principles and Practices of Interconnection Networks.",   San Mateo, CA, USA: Morgan Kaufmann   ,2004
View Artical


?R. Ezz-Eldin, M. A. El-Moursy, and H. F. A. Hamed, ,   "Novel routing algorithm for minimum on delay with process variation and congestion in asynchronous N",    IEEE Int. Conf. High Perform. Commun.   ,2015
View Artical


Y. Nakata, H. Kawaguchi, and M. Yoshimoto,   "A process-variationadaptive network-on-chip with variable-cycle routers and variable-cycle pipeline ",    IEICE Trans. Electron   ,Vol.95   ,Issue 4   ,2012
View Artical